A DRAM is a memory element which holds and supplies information for use by electronic computing and logic elements, such as microcontrollers, microprocessors, logic arrays, and the like. An ASIC or a SLIC is a single IC which includes a combination of various electronic components, such as microcontrollers, microprocessors, logic gates, registers, amplifiers and the like, all of which have been selected, connected and integrated together to perform specific functions for a specific application. Examples of SLICs are controllers for computer memory disc drives, graphics controllers, LAN switches, fuel injector control systems for internal combustion engines, global positioning systems, and control devices for a wide variety of consumer products, among many other things. SLICs are desirable for use in mass produced products because of the enormous amount of functionality which can be created at a very low effective cost. These types of SLICs are sometimes referred to as a "system on a chip," because of the complete functionality obtained from the single chip or IC.
DRAMs have only recently been incorporated as part of SLICs. Previously, when the SLIC required memory to function, separate memories or DRAM chips were provided on a printed circuit board. Embedding DRAM in a SLIC avoids the additional cost of a separate memory chip. Avoiding the cost of the separate DRAM chip is attractive when the SLIC itself requires only a small amount of memory, because separate DRAM chips are relatively costly and of considerable memory size.
The typical semiconductor fabrication process almost always creates some number of defective chips, simply because of the complexity of the fabrication process and the large number of variables which must be precisely controlled during the process to obtain a fully functional chip. The number of fully functional chips created relative to the number of chips started or attempted is known as the "yield." If the yield is high, a lower effective cost per functional chip results, since the cost per chip is inversely proportional to the yield. Because of the highly competitive nature of semiconductor fabrication business, it is essential to obtain the highest possible yield to keep the individual costs of each functional chip as low as possible.
Fabrication of a SLIC with an embedded DRAM typically presents a much higher risk of defects and lower yields than the fabrication of a SLIC without an embedded DRAM. The DRAM is formed by tens or hundreds of thousands of repetitive and closely spaced components, resulting in a very high "density" of elements. High densities inherently create a greater possibility of defects arising during fabrication. Thus, embedding a DRAM in a SLIC simply raises the risk of reduced yields and a higher effective cost for each of the functional SLICs produced.
The embedded DRAM portion of the SLIC usually represents a relatively small portion of the overall size of the typical SLIC. If this were not the case, it would be more cost effective to use a separate DRAM chip in combination with the SLIC. The impact of a defect arising from a defective DRAM portion of the SLIC is therefore typically much greater than its contribution toward the size and cost of the complete SLIC. It is perhaps for these reasons and others that DRAMs have not been embedded in SLICs on a widespread and commercial basis.
In contrast, commercial DRAM chips are fabricated with special DRAM fabrication processes that have been specifically developed to address the unique fabrication requirements of DRAMs. These DRAM processes have evolved over many years to improve density and enhance yields. However, these special DRAM processes are not particularly attractive for use in fabricating SLICs with embedded DRAMs, because many of the other non-DRAM components of the SLIC do not require or respond favorably to such special DRAM fabrication process. Thus, the special DRAM fabrication process is usually unnecessary and potentially expensive when applied to the remainder of the SLIC. The relative size contribution of the embedded DRAM to the overall size of the SLIC often will not justify the use of a special DRAM fabrication process, even if the DRAM fabrication process could be favorably applied to the remaining elements of the SLIC. Furthermore, the influences from the other non-DRAM components of the SLIC, such as noise, may require DRAM circuit designs which are not optimal for response to such special DRAM fabrication processes.
In order to address the defect problem in fabricating semiconductor chips, it is typical to include redundant elements. Upon detecting a defective element by testing after fabrication, the defective element is bypassed and one of the redundant elements is substituted in its place. In this manner the chip can be salvaged and made fully functional.
Redundancy is typically implemented by using a laser to explode or evaporate conductors formed in the chip, and thereby physically disconnect the defective components and substitute the functional redundant components. However, this laser programmed redundancy technique is not cost-effective in the circumstance of a relatively small size contribution of the embedded DRAM to the SLIC. The cost of the laser and the testing equipment is significant, as is time and costs to program and apply the laser to the minute pattern of DRAM conductors and components on the chip. A standard SLIC test environment must be maintained to test the SLIC, because of the high relative proportion of non-DRAM components and to assure proper functionality of the SLIC itself. If the costs of laser programmed redundancy were added to the standard SLIC test processes, the resulting test procedure would not be standard and could possibly escalate the costs of fabrication to the point of making the entire SLIC process cost-ineffective.
These considerations are further complicated by the differing requirements for embedded DRAM for a variety of different SLICs. Typically a SLIC manufacturer will have a "library" of standard component designs which can be incorporated together in creating the SLIC, because of the wide variety of different circuitry which may be required in different SLICs. The standard library designs will include, for example, arrays of logic gates, microprocessors, DRAMs and the like. The cost effectiveness of competing in the SLIC fabrication market depends on the ability to integrate the standard library designs together in creating the SLIC, without specifically having to redesign each component each time it is used in a different SLIC. Generally, successfully integrating different standard designs will require the ability to physically reposition the standard components on the chip to accommodate differing customer requirements. Furthermore, testing the SLIC is complicated by the different contributions and combinations of the standard designs, since a method must be devised to specifically test each component, even though the components may be combined in different patterns and relationships in different SLICs. Developing a unique test program for each different SLIC can also increase the overall costs of the SLIC.
Testing the SLIC is always accomplished initially after fabrication, and in addition, many SLICs also utilize a built in self test (BIST) to test the SLIC upon initially applying power. In general, the BIST program is executed to write a test pattern of signals to the DRAM array and thereafter to read the signals back from the DRAM array. The signals read from the array are compared with the signals which were written to the array, and the comparison reveals any defects in the DRAM. Each memory cell of the DRAM must be tested, and because a typical DRAM array has a large number of memory cells, BIST testing can occupy a considerable amount of time. While the BIST test occurs, the SLIC is not operational. BIST testing may delay the time when the SLIC becomes fully functional and able to respond in the environment in which it is intended to the used.
Substituting a redundant fully functional segment of a DRAM memory for a defective DRAM memory segment may also create difficulties in executing the operational software of the SLIC. The operational software maintains a memory map of the addresses of the functional memory, and these addresses are used by the software to achieve proper functionality. If a defective DRAM segment has one of the addresses in the range of the memory map, a memory remapper must be employed to translate the address signals generated by the operational software to the new address of the substituted redundant element. In general, memory remappers consume extra time to accomplish the address translation, and this extra time may degrade the performance of the SLIC. Thus, although redundancy may achieve a functional SLIC, the performance of the SLIC may suffer as a result of substituting those redundant elements which must be addressed during the normal functionality of the system software.
For all of the above reasons, and others, it is important to achieve high levels of performance from the DRAM embedded in SLICs and ICs, while using conventional SLIC manufacturing processes and redundancy techniques to fabricate the different types and configurations of SLICs. It is with respect to these and other considerations that the present invention has evolved.